R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 426

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
Page 396 of 1448
and transfer destination
Set number of transfers
Block transfer mode
Set transfer source
Read DMAECRF
Set MDLCFGCR
Figure 8.21 Example of Block Transfer Mode Setting Procedure
Set DMAECRF
Set DMAECRF
Block transfer
Set DMACRF
mode setting
addresses
(Common Register Disabled Mode)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[1] Clear the DMCOMMD bit in MDLCFGCR to 0.
[2] Set each bit in DMAECRF.
[3] Set the transfer source address in SAR and transfer
[4] Set the block size in both ETCRAH and ETCRAL.
[5] Set each bit in DMACRF.
[6] Read DTE = 0 and DTME = 0 in DMAECRF.
[7] Set each bit in DMAECRF.
destination address in DAR.
Set the number of transfers in ETCRB.
•
•
• Specify enabling or disabling of internal interrupt
• Set the transfer data size with the DTSZ bit.
• Specify whether SAR is to be incremented,
• Set the BLKE bit to 1 to select block transfer mode.
• Specify whether the transfer source or the transfer
• Specify whether DAR is to be incremented,
• Select the activation source with bits DTF3 to DTF0.
clearing with the DTA bit.
decremented, or fixed, with the SAID and SAIDE bits.
destination is a block area with the BLKDIR bit.
decremented, or fixed, with the DAID and DAIDE bits.
to the CPU with DTIE bit.
transfer.
Specify enabling or disabling of transfer end interrupts
Set both the DTME and DTE bits to 1 to enable
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010