R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 117

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
4
3
2
1
0
Bit Name
⎯
FLSHE
⎯
EXPE
RAME
Initial Value
0
0
0
⎯
1
R/W
R/W
R/W
⎯
R/W
R/W
Descriptions
Reserved
The initial value should not be modified.
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMDBPR, and FLMSTR). If this
bit is set to 1, the flash memory control registers can
be read from and written to. If this bit is cleared to 0,
the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are retained. 0 should be written to this bit in
LSIs other than the flash memory version.
0: Flash memory control registers are not selected for
1: Flash memory control registers are selected for
Reserved
This bit is always read as 0 and cannot be modified.
External Bus Mode Enable
Sets the external bus mode. In modes 1, 2, and 4,
this bit is fixed at 1 and cannot be modified. In modes
3, 5, and 7, this bit can be read from and written to.
Writing 0 to this bit when its value is 1 should only be
carried out when an external bus cycle is not being
executed.
0: External address space is disabled
1: External address space is enabled
RAM Enable
Enables or disables the on-chip RAM. This bit is
initialized when the reset state is canceled.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
addresses H'FFFEB0 to H'FFFEB3
addresses H'FFFEB0 to H'FFFEB3
Section 3 MCU Operating Modes
Page 87 of 1448