R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1054

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 17 I
Page 1024 of 1448
Note: * Ensure that no interrupts are received while steps [1] through [3] are being processed.
Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1],
2
No
No
No
C Bus Interface 2 (IIC2)
Set ACKBT = 0 (ICIER)
Set ACKBT = 1 (ICIER)
Set RCVD = 1 (ICCRA)
Set RCVD = 0 (ICCRA)
Set MST = 0 (ICCRA)
Set TRS = 0 (ICCRA)
Clear TEND in ICSR
Clear TDRE of ICSR
Dummy read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Clear STOP in ICSR
Read STOP of ICSR
Mater receive mode
Write BBSY = 0
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
and SCP = 0
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
End
- 1?
Figure 17.15 Sample Flowchart for Master Receive Mode
Yes
Yes
Yes
No
and processing jumps to step [7]. Step [8] is ICDDR dummy read.
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear STOP flag.
[11] Stop condition issuance.
[12] Wait for the generation of stop condition.
[13] Read the receive data of the final byte.
[14] Clear RCVD to 0.
[15] Set slave receive mode.
Clear TEND, select master receive mode, and then clear TDRE. *
Set acknowledge to the transmitting device. *
Dummy read ICDDR. *
Wait for 1 byte to be received.
Check if the (last receive - 1).
Read the receive data.
Set acknowledge of the final byte. Disable continuous receive (RCVD = 1).
Read receive data of (final byte - 1).
Wait for the final byte to be received.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010