R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 472

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 9 EXDMA Controller (EXDMAC)
9.3.5
EDACR specifies address register incrementing/decrementing and use of the repeat area function.
Page 442 of 1448
Bit
15
14
13
Bit Name
SAT1
SAT0
SARIE
EXDMA Address Control Register (EDACR)
0
0
0
Initial Value
R/W
R/W
R/W
R/W
Description
Source Address Update Mode
These bits specify incrementing/decrementing of
the transfer source address (EDSAR). When an
external device with DACK is designated as the
transfer source in single address mode, the
specification by these bits is ignored.
0x: Fixed
10: Incremented (+1 in byte transfer, +2 in word
11: Decremented (–1 in byte transfer, –2 in word
Source Address Repeat Interrupt Enable
When this bit is set to 1, in the event of source
address repeat area overflow, the IRF bit is set to
1 and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU.
When used together with block transfer mode, a
source address repeat interrupt is requested at the
end of a block-size transfer. If the EDA bit is set to
1 in EDMDR for the channel on which transfer is
terminated by a source address repeat interrupt,
transfer can be resumed from the state in which it
ended. If a source address repeat area has not
been designated, this bit is ignored.
0: Source address repeat interrupt is not
1: When source address repeat area overflow
requested
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested
transfer)
transfer)
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010