SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1093

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6249I–ATARM–3-Oct-11
Revision
6249D
Comments
Overview:
”Features”
Section 5.1 ”Power
Section 5.2 ”Power
Section 10.5.8 ”Multimedia Card
Section 8.2.1.1 ”External Bus Interface
Section 8.2.1.2 ”External Bus Interface 1”
”Package and
Figure 9-3, “AT91SAM9263 Power Management Controller Block Diagram,” on page
removed.
Section 10.5.8 ”Multimedia Card
Bus Matrix:
Section 20.5 ”Bus Matrix (MATRIX) User
only.
Section 20.5.5 ”Bus Matrix Master Remap Control
described.
Boot:
defined.
EBI:
(PMC_PLLICPR) removed.
”AT91SAM9263 Electrical Characteristics”
Table 47-2, ”DC Characteristics”
and
Table 47-2, ”DC
Table 47-10, ”32 kHz Oscillator Characteristics”, on page
Section 47.6.2 “32 kHz Crystal Characteristics” on page
Section 47.8 ”EBI
”AT91SAM9263 Errata”
Section 50.2 ”AT91SAM9263 Errata - Revision “A” Parts”
”CAN”,
Mailbox error on TX, removed from errata.
Section 50.2.9 ”LCD”
”MCI”,
Number of
Section 50.2.13.2 ”Mobile SDRAM Device Initialization
”Serial Peripheral Interface (SPI)” Section 50.2.15.1 ”SPI: PDC Data Loss”
Section 50.2.15.8 ”SPI: Bad Serial Clock Generation on 2nd Chip
”Power Management Controller (PMC) User Interface”
Figure 48-1, “324-ball TFBGA Package Drawing,” on page
”AT91SAM9263 Mechanical
Table 21-4, ”EBI Pins and External Static Devices
Section 13.8 ”Hardware and Software
Section 50.2.10.3 ”Data Timeout Error
Section 50.2.6.2 ”CAN: Low Power Mode and Pending Transmit Messages”
SPI: Synchronous Communications feature removed.
Bytes”,
Pinout”, references to package are “324-ball TFBGA”
Characteristics”, VIL, VIH, VOL, VOH, conditions updated
Timings”, tables and figures pertinent to the SMC in this section have been updated.
Section 50.2.10.5 ”Flag Reset is not correct in half duplex mode”
Supplies”, VDDIO and VDDBU slope alignment described.
Consumption”, paragraph beginning with “On VDDBU...” updated.
added to errata
Interface”,”When REMAP = 1.....” removed from 2nd paragraph.
Interface”, MMC and SDMC compatibility updated.
Reference to Junction Temperature removed.
Characteristics”, Thermal Considerations removed.
0”, feature added.
Interface”, MATRIX_PRASx and MATRIX_PRBSx are Write-
feature added.
and
Constraints”, internal SRAM constraints and user area are
Flag”,
”AT91SAM9263 Mechanical Characteristics”
Register”, remap control bits and masters are
Section 50.2.10.4 ”Data Write Operation and
Constraint”, updated.
PLL CHarge Pump Current Register
Connections”, NCS2/NANDCS signals defined.
1033, added.
1033, removed VDDOSC = 1.2V
1056, updated.
Select”, added.
updated.
updated.
added
30, /3 divider
AT91SAM9263
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