SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1067

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.2.15.5
50.2.15.6
50.2.15.7
50.2.15.8
6249I–ATARM–3-Oct-11
SPI: Baudrate set to 1
SPI: Software Reset
SPI: Chip Select and Fixed Mode
SPI: Bad Serial Clock Generation on 2nd Chip Select
Use the CS in PIO mode when PDC Mode is required and CS has to be maintained between
transfers.
When Baudrate is set to 1 (i.e. when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No such pulse occurs if BITS
field equals 8,10,12,14 or 16 and Baudrate = 1.
None.
If the Software reset command is performed during the same clock cycle as an event for
TXRDY, there is no reset.
Perform another a software reset.
In fixed Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip
Select 0, the output spi_size sampled by the PDC depends on the field BITS of SPI_CSR0 reg-
ister, whatever the selected Chip select may be. For example, if CSR0 is configured for a 10-bit
transfer, whereas the CSR1 is configured for an 8-bit transfer, when a transfer is performed in
Fixed mode through the PDC on Chip Select 1, the transfer is considered to be a half-word
transfer.
If a PDC transfer has to be performed in 8 bits on a Chip select y (y different from 0), the field
BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy
Register.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9263
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