SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 282

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

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AT91SAM9263
Figure 25-6. Multi-Block with Linked List Address for Source and Destination
If the user needs to execute a DMA transfer where the source and destination address are con-
tiguous but the amount of data to be transferred is greater than the maximum block size
DMAC_CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as
shown in
matically reprograms the DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx
channel registers. The DMA transfer continues until the DMAC determines that the
DMAC_CTLx and DMAC_LLPx registers at the end of a block transfer match that
described in Row 1 of
ous block transferred was the last block in the DMA transfer. The DMA transfer might
look like that shown in
Source Layer
Address of
Figure 25-7 on page
SAR(2)
SAR(1)
SAR(0)
Source Blocks
Table 25-2 on page
Figure 25-6 on page
283.
Block 1
Block 2
Block 0
DAR(2)
DAR(1)
277. The DMAC then knows that the previ-
DAR(0)
282.
Destination Blocks
Block 1
Block 2
Block 0
Destination Layer
Address of
6249I–ATARM–3-Oct-11