SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 29

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

9.2
9.3
9.4
Figure 9-2.
6249I–ATARM–3-Oct-11
Reset Controller
Shutdown Controller
Clock Generator
Clock Generator Block Diagram
• Based on two Power-on-Reset cells
• Status of the last reset
• Controls the internal resets and the NRST pin output
• Shutdown and Wake-up logic
• Embeds the low-power 32768 Hz Slow Clock Oscillator
• Embeds the Main Oscillator
• Embeds 2 PLLs
– One on VDDBU and one on VDDCORE
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
– Allows shaping a reset signal for the external devices
– Software programmable assertion of the SHDN pin (SHDN is push-pull)
– Deassertion programmable on a WKUP pin level change or on alarm
– Provides the permanent Slow Clock SLCK to the system
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
– Output 80 to 240 MHz clocks
– Integrates an input divider to increase output accuracy
– 1 MHz Minimum input frequency
reset, user reset or watchdog reset
XOUT32
PLLRCA
PLLRCB
XIN32
XOUT
XIN
Clock Generator
Management
Slow Clock
Controller
Oscillator
Oscillator
Status
PLL and
Divider A
PLL and
Divider B
Power
Main
Control
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
AT91SAM9263
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