SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 317

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.4.13
Name: DMAC_MaskTfr, DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr
Address:0x00800310
Address:0x00800318
Address:0x00800320
Address:0x00800328
Address:0x00800330
Access: Read-write
Reset: 0x0
The contents of the Raw Status Registers are masked with the contents of the Mask Registers: DMAC_MaskTfr,
DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr. Each Interrupt Mask register has a bit
allocated per channel, for example, DMAC_MaskTfr[2] is the mask bit for Channel 2’s transfer complete interrupt.
A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted
on the same AMBA write transfer. This allows software to set a mask bit without performing a read-modified write
operation.
For example, writing hex 01x1 to the DMAC_MaskTfr register writes a 1 into DMAC_MaskTfr[0], while DMAC_MaskTfr[7:1]
remains unchanged. Writing hex 00xx leaves DMAC_MaskTfr[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMAC to set the appropriate
bit in the Status Registers.
• INT_MASKx: Interrupt Mask
0 = Masked
1 = Unmasked
• INT_M_WEx: Interrupt Mask Write Enable
0 = Write disabled
1 = Write enabled
6249I–ATARM–3-Oct-11
31
23
15
–
–
–
7
–
Interrupt Status Registers
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
INT_M_WE1
INT_MASK1
AT91SAM9263
25
17
–
–
9
1
INT_M_WE0
INT_MASK0
24
16
–
–
8
0
317