SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1075
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 1075 of 1109
- Download datasheet (17Mb)
50.3.8
50.3.8.1
6249I–ATARM–3-Oct-11
LCD
LCD Screen Shifting After a Reset
EMACB master interface releases the AHB bus between two transfers.
EMACB has the highest priority.
If we are in a state where EMACB RX and TX FIFOs have requests pending, the following
sequence occurs:
In a case of a slow memory and/or a special operation such as SDRAM refresh or SDRAM bank
opening /closing, there may be TX underrun (latency min 960 ns).
Reduce re-arbitration time between RX and TX EMACB transfer by using internal SRAM (or
another slave with a short access time) for transmit buffers and descriptors.
When a FIFO underflow occurs, a reset of the DMA and FIFO pointers is necessary. Performing
the following sequence:
lead to well reset DMA pointers but not FIFO pointers, the displayed image is shifted.
Apply the following sequence:
1. Receive buffer manager write
2. Receive buffer manager read
3. Transmit data DMA read
4. Receive data DMA write
5. Transmit buffer manager read
6. Transmit buffer manager write
1. EMACB RX FIFO write (burst 4)
2. EMACB release the AHB bus
3. The AHB matrix can grant an another master (ARM I or D for example)
4. AHB matrix re-arbitration (finish at least the current word/halfword/byte)
5. The AHB matrix grants the EMACB
6. The EMACB TX FIFO read (burst 4)
• DMA disable
• Wait for DMABUSY
• DMA reset
• DMA enable
• LCD power off
• DMA disable
• Wait for DMABUSY
• DMA reset
• LCD power on
• DMA enable.
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9263
1075
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