SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1095

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6249I–ATARM–3-Oct-11
Revision
6249C
Comments
In
All new information for
Slaves,” on page 17
In
In
Corrected
In
list of EBI1.
In
removed mention of keyboard interfaces.
In
Boot: Updated supported crystals in
(MHz),” on page
Corrected
Updated supported DataFlash device references in
EBI: Updated
“Organization of the External Bus Interface 1,” on page 165
Devices Connections,” on page 170
ALE NAND Flash signals. Removed reference to EBI0 for NANDOE and NANDWE.
In
In
I/O. Added Note
SHDW: In
SMC: In
Byte Write Access mode.
ECC:
Section 24.3.1 “Write Access” on page 258
Section 24.4.4 “ECC Parity Register” on page 266
267
In
PMC: In
PIO: Notes
SPI: In
TWI: New
Section 10.4.3 “EBI1” on page
Table 21-5, “EBI Pins and External Devices Connections,” on page
Section 4.1 “324-ball TFBGA Package Outline” on page 10
Section 9.3 “Shutdown Controller” on page
Section 5.2 “Power Consumption” on page
Section 10.4.11 “Image Sensor Interface” on page 42
Table 12-3, ”AT91SAM9263 JTAG Boundary Scan Register”
Table 21-2, “EBI1 I/O Lines Description,” on page
Table 24-1, “Register Mapping,” on page
updated.
Section 24.3 “Functional Description” on page 258
Section 32.6.4 “SPI Slave Mode” on page
Section 22.7.2.1 “Byte Write Access” on page
Section 28.3 “Processor Clock Controller” on page
Section 10.4.7 “NAND Flash” on page
Figure 13-3, “LDR Opcode,” on page
Section 33. “Two-wire Interface (TWI)” on page
Table 18-2, “Register Mapping,” on page
(1)
,
Figure 21-1, “Organization of the External Bus Interface 0,” on page 164
(2)
(5)
97.
and
on CE and NAND Flash.
and
(3)
Table 7-1, “List of Bus Matrix Masters,” on page
updated in
Table 7-3, “Masters to Slaves Access,” on page
41, added Ethernet 10/100 MAC to the System Resource Multiplexing
Table 31-2, “Register Mapping,” on page
with NANDALE and NANDCLE pins. Removed note on CLE and
Table 13-1, “Crystals Supported by Software Auto-detection
and
262, corrected offset value for ECC_SR.
13, specified static current consumption as worst case.
29, corrected reference to shutdown pin.
98.
Section 24.3.2 “Read Access” on page 258
41, with information on EMAC.
461, updated information on OVRES
and
Table 13-2, “DataFlash Device,” on page
145, corrected offset value for SHDW_SR register.
167, corrected EBI address bus width.
195, added information that boot is not allowed in
Section 24.4.5 “ECC NParity Register” on page
and
updated.
481.
and
349, new details on PCK disable.
Section 10.4.12 “Timers” on page
corrected package top view.
on
Table 21-5, “EBI Pins and External
page
170, corrected NAND Flash AD to
16,
86, changed pin 246 to NC.
18.
Table 7-2, “List of Bus Matrix
434.
and
bit.
AT91SAM9263
Figure 21-2,
updated.
99.
42,
Change
Request
Ref.
4463
4466
3870
3825
4064
4407
4230
4450
4186
4149
3850
3905
4224
3252
3970
4306
3835
3974
3943
1095