SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1046

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

47.8.4.2
Table 47-29. SDRAMC Clock Signal
Table 47-30. SDRAMC Signals
Note:
1046
Symbol
1/(t
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
CPSDCK
1. The derating factor is not to be applied to t
AT91SAM9263
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
)
External Bus Interface 1 Timings
Parameter
SDCKE High before SDCK Rising Edge
SDCKE Low after SDCK Rising Edge
SDCKE Low before SDCK Rising Edge
SDCKE High after SDCK Rising Edge
SDCS Low before SDCK Rising Edge
SDCS High after SDCK Rising Edge
RAS Low before SDCK Rising Edge
RAS High after SDCK Rising Edge
SDA10 Change before SDCK Rising Edge
SDA10 Change after SDCK Rising Edge
Address Change before SDCK Rising Edge
Address Change after SDCK Rising Edge
Bank Change before SDCK Rising Edge
Bank Change after SDCK Rising Edge
CAS Low before SDCK Rising Edge
CAS High after SDCK Rising Edge
DQM Change before SDCK Rising Edge
DQM Change after SDCK Rising Edge
D0-D15 in Setup before SDCK Rising Edge
D0-D15 in Hold after SDCK Rising Edge
D16-D31 in Setup before SDCK Rising Edge
D16-D31 in Hold after SDCK Rising Edge
SDWE Low before SDCK Rising Edge
SDWE High after SDCK Rising Edge
D0-D15 Out Valid before SDCK Rising Edge
D0-D15 Out Valid after SDCK Rising Edge
D16-D31 Out Valid before SDCK Rising Edge
D16-D31 Out Valid after SDCK Rising Edge
Parameter
SDRAM Controller Clock Frequency
VDDCORE supply
VDDIOM supply
CLMCK
or t
CHMCK
1.08V
-0.2
3.6
4.3
3.8
3.7
3.7
4.2
4.7
3.0
4.0
3.7
3.2
3.8
3.4
3.8
4.7
3.0
3.3
3.8
0.7
0.6
2.1
4.2
3.6
3.2
3.1
3.9
3.4
.
1.8V
1.8V Supply
100
1.2V
-0.2
3.9
4.4
4.1
3.9
4.0
4.2
4.8
3.4
4.3
3.8
3.6
3.9
3.8
3.8
4.8
3.4
3.6
3.8
0.5
0.5
1.5
3.4
3.7
3.7
3.4
4.2
3.6
Min
Max
1.08V
-0.1
2.3
5.1
2.2
4.8
2.0
5.0
3.1
4.1
2.7
4.8
1.7
4.3
1.8
4.3
3.1
4.1
1.7
4.3
0.8
0.7
2.2
2.5
4.7
1.7
4.1
2.4
4.5
3.3V Supply
3.3V
100
1.2V
-0.1
2.8
5.1
2.6
4.8
2.5
5.0
3.4
4.3
3.1
4.7
2.4
4.3
2.4
4.3
3.4
4.3
2.2
4.3
0.5
0.6
1.6
2.9
4.7
2.3
4.1
2.8
4.5
6249I–ATARM–3-Oct-11
Units
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns