SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 280

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.3.5.3
280
AT91SAM9263
Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10)
4. After the DMAC selected channel has been programmed, enable the channel by writing
5. Source and destination request single and burst DMA transactions to transfer the block
6. Once the transfer completes, hardware sets the interrupts and disables the channel. At
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory.
– ii. Set up the transfer characteristics, such as:
e. Write the channel configuration information into the DMAC_CFGx register for chan-
– i. Designate the handshaking interface type (hardware or software) for the source
– ii. If the hardware handshaking interface is activated for the source or destination
f.
g. If scatter is enabled (DMAC_CTLx.D_SCAT_EN, program the DMAC_DSRx regis-
a ‘1’ to the DMAC_ChEnReg.CH_EN bit. Make sure that bit 0 of the
DMAC_DmaCfgReg register is enabled.
of data (assuming non-memory peripherals). The DMAC acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
this time you can either respond to the Block Complete or Transfer Complete interrupts,
or poll for the Channel Enable (DMAC_ChEnReg.CH_EN) bit until it is cleared by hard-
ware, to detect when the transfer is complete.
Write the control information in the LLI.DMAC_CTLx register location of the block
descriptor for each LLI in memory (see
example, in the register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests.
Writing a ‘1’ activates the software handshaking interface to handle
source/destination requests.
peripheral, assign a handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
nel x.
If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the
DMAC_SGRx register for channel x.
ter for channel x.
nation) and flow control device by programming the TT_FC of the DMAC_CTLx
register.
Figure 25-8 on page
284) for channel x. For
6249I–ATARM–3-Oct-11