SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 303

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.4.2
Name: DMAC_DARx
Addresses:0x00800008 [0], 0x00800060 [1]
Access: Read-write
Reset: 0x0
The address offset for each channel is: 0x08+[x * 0x58]
For example, DAR0: 0x008, DAR1: 0x060, etc.
• DADD: Destination Address of DMA transfer
The starting AMBA destination address is programmed by software before the DMA channel is enabled or by a LLI update
before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the destination
address of the current AMBA transfer.
Updated after each destination AMBA transfer. The DINC field in the DMAC_CTLx register determines whether the
address increments, decrements or is left unchanged on every destination AMBA transfer throughout the block transfer.
6249I–ATARM–3-Oct-11
31
23
15
7
Channel x Destination Address Register
30
22
14
6
29
21
13
5
28
20
12
4
DADD
DADD
DADD
DADD
27
19
11
3
26
18
10
2
AT91SAM9263
25
17
9
1
24
16
8
0
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