SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 289

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6249I–ATARM–3-Oct-11
17. The DMAC reloads the DMAC_SARx register from the initial value. Hardware sets the
18. The DMA transfer proceeds as follows:
19. The DMAC fetches the next LLI from memory location pointed to by the current
block complete interrupt. The DMAC samples the row number as shown in
on page
ware sets the transfer complete interrupt and disables the channel. You can either
respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel
Enable (DMAC_ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when
the transfer is complete. If the DMAC is not in Row 1 or 5 as shown in
page 277
a. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete inter-
b. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt
DMAC_LLPx register, and automatically reprograms the DMAC_DARx, DMAC_CTLx
and DMAC_LLPx channel registers. Note that the DMAC_SARx is not re-programmed
as the reloaded value is used for the next DMA block transfer. If the next block is the last
block of the DMA transfer then the DMAC_CTLx and DMAC_LLPx registers just fetched
from the LLI should match Row 1 of
look like that shown in
rupt is un-masked (DMAC_MaskBlock[x] = 1’b1, where x is the channel number)
hardware sets the block complete interrupt when the block transfer has completed.
It then stalls until the block complete interrupt is cleared by software. If the next
block is to be the last block in the DMA transfer, then the block complete ISR (inter-
rupt service routine) should clear the DMAC_CFGx.RELOAD_SR source reload
bit. This puts the DMAC into Row1 as shown in
block is not the last block in the DMA transfer, then the source reload bit should
remain enabled to keep the DMAC in Row 7 as shown in
is masked (DMAC_MaskBlock[x] = 1’b0, where x is the channel number) then hard-
ware does not stall until it detects a write to the block complete interrupt clear
register but starts the next block transfer immediately. In this case, software must
clear the source reload bit, DMAC_CFGx.RELOAD_SR, to put the device into Row
1 of
completed.
Table 25-2 on page 277
277. If the DMAC is in Row 1 or 5, then the DMA transfer has completed. Hard-
the following steps are performed.
Figure 25-11 on page
before the last block of the DMA transfer has
Table 25-2 on page
290.
Table 25-2 on page
277. The DMA transfer might
Table 25-2 on page
AT91SAM9263
Table 25-2 on
277. If the next
Table 25-2
277.
289