SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1090

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

1090
Revision
6249E
AT91SAM9263
Comments (Continued)
DMAC:
Figure 25-4, “External DMA Request Timing,” on page
Section 25.3.3.5 ”External DMA Request
ends...” added to 4th paragraph.
Multiple bits represented by “x” in Bit names from
327
Section 25.4.7 ”Configuration Register for Channel x
previous paragraph.
Section 25.4 ”DMA Controller (DMAC) User
address 0x3a4, 0x3b8 is reserved.
Debug and Test
Figure 12-6, “AMP Mictor Connector
Table 12-3, ”AT91SAM9263 JTAG Boundary Scan
updated for bit 203.
EMAC:
Section 41.3.1 ”Clock”
GPBR:
The General Purpose Backup Registers section has been added.
ISI:
Section 46.4.7 ”ISI Preview
LCDC:
Section 44.10.2 ”TFT Mode
MCI:
Section 40.1
PMC and CKGR:
Section 28.1
Section 28.3 ”Processor Clock
Figure 27-1, “Typical Slow Clock Crystal Oscillator
Section 27.4.2 ”Divider and Phase Lock Loop
initialization.
Section 28.7 ”Programming
in step 3: “Setting PLLA and divider A”, ICPPLA requirement added to 1st paragraph.
in step 4: “Setting PLLB and divider B”, ICPPLB requirement added to 1st paragraph.
Section 28.7 ”Programming
in step 6, “Selection of Master CLock and Processor Clock”, 4th paragraph, this text has been added: “By
default, the PRES parameter is set to 0 which means that master clock is equal to slow clock.”
PWM:
Section 38.6 ”Pulse Width Modulation Controller (PWM) User
indexed. (see
Section 38.6.13 ”PWM Channel Update Register”
RSTC:
Section 14.3.4.4 ”Software
”Overview”, MCI supports Multimedia Card (MMC) Specification V3.31
”Overview”: “PCK must be switched off........”
Table 38-2 on page
added to Functional Description
Reset”, PERRST must be used with PROCRST, except for debug purposes.
Register”: PREV_HSIZE and PREV_VSIZE updated with RGB only comments.
Example”, “HFP....” line, typo corrected: “HPW = (64-2)”
Sequence”;
Sequence”;
Controller”, new information added explaining Idle Mode.
719)
Orientation”, replaced internal product reference in figure.
Definition”, 3rd paragraph CTLxL.xxx typos fixed. “The DMA
Interface”, DMA_IdReg, DMAC_DmaTestReg removed.
Programming”, added the last line, specific to PLLA and PLLB
Section 25.4.11 on page 315
Fixed typos in table: CPD (PWM_CMRx Register)
Register”, pin names assigned to bits 517, 205. pin name
Connection”, corrected GNDPLL to GNDBU
High”, SRC_PER bitfield description unscrambled from
275, updated.
Interface”, Channel-dependent registers are
to
Section 25.4.23 on page
6249I–ATARM–3-Oct-11
Change
Request
Ref.
5503
rfo
5504
5524
5644
5385
5607
3328
rfo
5430
5619
5282
4322
4470
5046
5596
4486
5185
5436