SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 196
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 196 of 1109
- Download datasheet (17Mb)
23.5
23.5.1
Figure 23-2. Write Burst, 32-bit SDRAM Access
SDRAMC_A[12:0]
23.5.2
6249I–ATARM–3-Oct-11
D[31:0]
SDWE
SDCS
SDCK
Functional Description
RAS
CAS
SDRAM Controller Write Cycle
SDRAM Controller Read Cycle
Row n
The SDRAM Controller allows burst access or single access. In both cases, the SDRAM control-
ler keeps track of the active row in each bank, thus maximizing performance. To initiate a burst
access, the SDRAM Controller uses the transfer type signal provided by the master requesting
the access. If the next access is a sequential write access, writing to the SDRAM device is car-
ried out. If the next access is a write-sequential access, but the current access is to a boundary
page, or if the next access is in another row, then the SDRAM Controller generates a precharge
command, activates the new row and initiates a write command. To comply with SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (t
active/write (t
Configuration Register” on page
The SDRAM Controller allows burst access, incremental burst of unspecified length or single
access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus
maximizing performance of the SDRAM. If row and bank addresses do not match the previous
row/bank address, then the SDRAM controller automatically generates a precharge command,
activates the new row and starts the read command. To comply with the SDRAM timing param-
eters, additional clock cycles on SDCK are inserted between precharge and active commands
(t
uration register of the SDRAM Controller. After a read command, additional wait states are
generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration
register).
RP
) and between active and read command (t
t
RCD
= 3
col a
RCD
Dna
) commands. For definition of these timing parameters, refer to the
col b
Dnb
col c
Dnc
249. This is described in
col d
Dnd
col e
Dne
RCD
col f
Dnf
). These two parameters are set in the config-
col g
Dng
Figure 23-2
col h
Dnh
AT91SAM9263
col i
Dni
below.
col j
Dnj
RP
) commands and
col k
Dnk
“SDRAMC
col l
Dnl
238
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