SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1096

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

1096
Revision
6249C
AT91SAM9263
Comments
USART: In
In
reset.
CAN: In
UDP:
Updated description of bit EPEDS in the USB_CSR register on
not affected.
Updated: write
Updated: write 0
LCDC: In
Updated
format.
Updated bit description
configuration table with new value for 24 bpp unpacked.
In
occurrences of “pin” to “signal”.
ISI: Added information to CODEC_ON bit description in
1006.
Added Bit 3 CDC_PND to
Correction to name of
Added note on ISI_PCK to
Updated ISI_RST bit description in
In
Added
Updated
Corrected VDDOSC value in
Errata changes: Inserted
on page
Inserted
Updated
Inserted
Inserted
Inserted
on page
Inserted
Section 34.6.2 “Receiver and Transmitter Control” on page
Section 44.11.24 “Power Control Register” on page
Table 47-3, “Power Consumption for Different Modes,” on page
Table 43-2 on page
Table 47-7, “Master Clock Waveform Parameters,” on page
Figure 37-7 on page 660
1060.
“EMACB”
“USART”
“SDRAM Controller”
Section 50.2.11.1 “NTRST: Device does not boot correctly due to power-up sequencing issue”
1064.
Section 50.2.4.1 “BMS Does Not Have Correct State” on page
Table 44-4, ”Little Endian Memory Organization”, on page
Section 47.6 “Crystal Oscillator Characteristics” on page
“USART”
Table 44-1, “I/O Lines Description,” on page
Section 34.5.1 “I/O Lines” on page 521
1=.....”RX_DATA_BK0: Receive Data Bank
=...”TXPKTRDY: Transmit Packet Ready”
,
,
,
Section 50.2.21.1 “SCK1 and SCK2 are Inverted” on page
Section 50.2.8.1 “Transmit Underrun Errors” on page
Section 49.2.19.3 “CTS Signal in Hardware Handshake” on page
Section 46.4.8 “ISI Preview Decimation Factor Register” on page
”PIXELSIZE: Bits per pixel” on page 938
“Two D Graphic Controller (TDGC)”
863, “Supported Endpoint” column updated in the USB Communication Flow.
Section 46.4.3 “ISI Status Register” on page
Table 46-9, “Register Mapping,” on page
Table 47-10, “32 kHz Oscillator Characteristics,” on page
,
Section 50.2.13.3 “JEDEC Standard Compatibility” on page
corrected mode switch conditions.
Section 46.4.1 “ISI Control 1 Register” on page
added information on TXD enabled.
947, LCD_PWR bit description, changed all
899, updated description of LCDDEN.
Section 46.4.1 “ISI Control 1 Register” on page
0”bitfield in USB_CSR
bitfield in USB_CSR
,
527, corrected information on software
page 894
Section 50.2.2.1 “Polygon Fill Function”
in LCDCON2 register, updated bit
1033.
1027, added note for SRAM access.
1031.
903, with Pixel 24 bpp unpacked
1005.
1010.
1060.
for details on control endpoints
1062.
1071.
1006.
1038.
1033.
1017.
1065.
6249I–ATARM–3-Oct-11
Change
Request
Ref.
4825
4367
4089
3476
4063
4099
3587
3518
3519
3250
3524
3904
4304
4092,
3862
4244
4093
4093
4093
4465
4221
3882