SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 273

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.3.2
25.3.3
25.3.3.1
25.3.3.2
6249I–ATARM–3-Oct-11
Memory Peripherals
Handshaking Interface
Software Handshaking
Burst Transactions
known as pseudo fly-by operation. For this to occur, the master interface for both source and
destination layers must win arbitration of their AHB layer. Similarly, the source and destination
peripherals must win ownership of their respective master interfaces.
Figure 25-3 on page 271
eral. There is no handshaking interface with the DMAC, and therefore the memory peripheral
can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately
without waiting for a transaction request. The alternative to not having a transaction-level hand-
shaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the
channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait
states onto the bus until it is ready; it is not recommended that more than 16 wait states be
inserted onto the bus. By using the handshaking interface, the peripheral can signal to the
DMAC that it is ready to transmit/receive data, and then the DMAC can access the peripheral
without the peripheral inserting wait states onto the bus.
Handshaking interfaces are used at the transaction level to control the flow of single or burst
transactions. The operation of the handshaking interface is different and depends on whether
the peripheral or the DMAC is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to trans-
fer/accept data over the AMBA bus. A non-memory peripheral can request a DMA transfer
through the DMAC using one of two handshaking interfaces:
Software selects between the hardware or software handshaking interface on a per-channel
basis. Software handshaking is accomplished through memory-mapped registers, while hard-
ware handshaking is accomplished using a dedicated handshaking interface.
When the slave peripheral requires the DMAC to perform a DMA transaction, it communicates
this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMA trans-
action. These software registers are used to implement the software handshaking interface.
The HS_SEL_SRC/HS_SEL_DST bit in the DMAC_CFGx channel configuration register must
be set to enable software handshaking.
When the peripheral is not the flow controller, then the last transaction registers
DMAC_LstSrcReg and DMAC_LstDstReg are not used, and the values in these registers are
ignored.
Writing a 1 to the DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] register is always interpreted as
a burst transaction request, where x is the channel number. However, in order for a burst trans-
a c t i o n
DMAC_SglReqSrcReg[x]/DMAC_SglReqDstReg[x] register.
• Hardware handshaking
• Software handshaking
r e q u e s t
t o
shows the DMA transfer hierarchy of the DMAC for a memory periph-
s t a r t ,
s o f t w a r e
m u s t
w r i t e
AT91SAM9263
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