SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 294

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 25-14. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination Address
25.3.5.7
294
AT91SAM9263
Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)
DMAC Transfer Complete
interrupt generated here
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the LLI. DMAC_CTLx
register location of the block descriptor for each LLI in memory for channel x. For exam-
ple, in the register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
Channel Disabled by
nation) and flow control device by programming the TT_FC of the DMAC_CTLx
register.
Block Complete interrupt
hardware
generated here
yes
interrupt cleared by software
DMAC State Machine Table?
Stall until Block Complete
MASKBLOCK[x]=1?
Channel Enabled by
Reload SARx, CTLx
Is DMAC in Row1 of
CTLx.INT_EN=1
Block Transfer
software
&&
no
yes
no
6249I–ATARM–3-Oct-11