SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1077

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.3.9.2
50.3.9.3
50.3.9.4
50.3.9.5
50.3.10
50.3.10.1
50.3.11
50.3.11.1
6249I–ATARM–3-Oct-11
NTRST
Reset Controller (RSTC)
SDIO interrupt does not work with slots other than A
Data Timeout Error Flag
Data Write Operation and Number of Bytes
Flag Reset is not correct in half duplex mode
NTRST: Device does not boot correctly due to power-up sequencing issue
RSTC: ERSTL Default Value is 1
If there is a 1-bit data bus width on other slots than Slot A, the SDIO interrupt cannot be cap-
tured. The sample is made on the wrong data line.
None
As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled wait-
ing indefinitely the Data start bit.
A STOP command must be sent with a software timeout.
The Data Write operation with a number of bytes less than 12 is impossible.
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be
incorrect.
These flags are reset correctly after a PDC channel enable.
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the
PDC channel by writing PDC_TXTEN or PDC_RXTEN.
The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is pow-
ered by VDDCORE power supply (1.2V).
During the power-up sequence, if VDDIOP power supply is not established whereas the
VDDCORE Power On Reset output is released, the NTRST signal is not correctly asserted. This
leads to a bad reset of the Embedded Trace Macrocell (ETM9). The ARM processor then enters
debug state and the device does not boot correctly.
The default value of ERSTL field in RSTC_MR register has been changed from 0x0 to 0x1. This
means that the NRST line rises 4 cycles after backup_nreset
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes
2. Connect NTRST to GND if no debug capabilities are required.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
place in all cases.
AT91SAM9263
1077