SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 775

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.7.2
6249I–ATARM–3-Oct-11
Data Transfer Operation
Figure 40-9. Command/Response Functional Flow Diagram
Note:
The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream,
etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI
Command Register (MCI_CMDR).
These operations can be done using the features of the Peripheral DMA Controller (PDC). If the
PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities.
In all cases, the block length (BLKLEN field) must be defined either in the mode register
MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block.
Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage
with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words,
otherwise the type of transfers are in bytes.
If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response
in the MultiMedia Card specification).
Check error bits in the
Wait for command
status register
ready status flag
(1)
Set the command argument
MCI_ARGR = Argument
Read response if required
MCI_CMDR = Command
Status error flags?
Set the command
Read MCI_SR
RETURN OK
CMDRDY
1
(1)
RETURN ERROR (1)
AT91SAM9263
Yes
0
775