SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1065

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.2.12
50.2.12.1
50.2.12.2
50.2.13
50.2.13.1
50.2.13.2
50.2.13.3
6249I–ATARM–3-Oct-11
ROM Code
SDRAM Controller
SDCard Boot is Not Functional
NAND Flash Boot is Not Functional
SDCLK Clock Active after Reset
Mobile SDRAM Device Initialization Constraint
JEDEC Standard Compatibility
leads to a bad reset of the Embedded Trace Macrocell (ETM9). The ARM processor then enters
debug state and the device does not boot correctly.
SDCard Boot is not functional in this revision.
None.
NAND Flash Boot is not functional in this revision.
None.
After a reset, the SDRAM clock is always active leading to overconsumption in the pad.
The following sequence stops the SDRAM clock:
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In the current configuration, SDCKE rises at the same time as SDCK while exiting self-refresh
mode. To be fully compliant with the JEDEC standard, SDCK must be STABLE before the rising
edge of SDCKE.
It is not the case in this product.
Use a fully JEDEC compliant SDRAM module.
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes
2. Connect NTRST to GND if no debug capabilities are required.
1. Set the bit LPCB in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
place in all cases.
complete.
AT91SAM9263
1065