SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 24

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 8-3.
Note:
8.1.1.2
8.1.2
8.1.2.1
24
Decoded
Area
SRAM C
Internal
(AHB)
1. Configuration after reset.
AT91SAM9263
Boot Strategies
Internal 16 Kbyte Fast SRAM
BMS = 1, Boot on Embedded ROM
Address
0x0030 0000
0x0030 4000
0x0030 8000
0x0030 C000
0x0031 0000
16 Kbyte Block Allocation (Continued)
When accessed from the Bus Matrix, the internal 80 Kbytes of Fast SRAM is single cycle acces-
sible at full matrix speed (MCK). When accessed from the processor’s TCM Interface, they are
also single cycle accessible at full processor speed.
The AT91SAM9263 integrates a 16 Kbyte SRAM, mapped at address 0x0050 0000. This SRAM
is single cycle accessible at full Bus Matrix speed.
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed with two parameters.
REMAP allows the user to layout the internal SRAM bank to 0x0. This is done by software once
the system has booted. Refer to the section “AT91SAM9263 Bus Matrix” in the product
datasheet for more details.
When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external
memory. This is done via hardware at reset.
Note:
The AT91SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin
BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
The system boots on Boot Program.
• Boot at slow clock
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
Configuration examples and related 16 Kbyte block assignments
ITCM = 0 Kbyte
DTCM = 0 Kbyte
AHB = 80 Kbytes
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in
RB4
RB3
RB2
RB1
RB0
(1)
ITCM = 32 Kbytes
DTCM = 32 Kbytes
AHB = 16 Kbytes
RB4
ITCM = 16 Kbytes
DTCM = 32 Kbytes
AHB = 32 Kbytes
RB4
RB0
Figure 8-1 on page
ITCM = 32 Kbytes
DTCM = 16 Kbytes
AHB = 32 Kbytes
RB4
RB2
21.
6249I–ATARM–3-Oct-11
ITCM = 16 Kbytes
DTCM = 16 Kbytes
AHB = 48 Kbytes
RB4
RB2
RB0