SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 229

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SAM9263

Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9263

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
22.8.5
Table 22-4.
6249I–ATARM–3-Oct-11
Coded Value
setup [5:0]
pulse [6:0]
cycle [8:0]
Coding Timing Parameters
Coding and Range of Timing Parameters
Number of Bits
Figure 22-15. WRITE_MODE = 0. The write operation is controlled by NCS
All timing parameters are defined for one chip select and are grouped together in one
SMC_REGISTER according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
Table 22-4
6
7
9
NWR0, NWR1,
NWR2, NWR3
NBS0, NBS1,
NBS2, NBS3,
A0, A1
D[31:0]
A
shows how the timing parameters are coded and their permitted range.
NWE,
[25:2]
MCK
NCS
256 x cycle[8:7] + cycle[6:0]
128 x setup[5] + setup[4:0]
256 x pulse[6] + pulse[5:0]
Effective Value
Coded Value
0 ≤ ≤ 127
0 ≤ ≤ 31
0 ≤ ≤ 63
Permitted Range
AT91SAM9263
Effective Value
0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
0 ≤ ≤ 128+31
0 ≤ ≤ 256+63
205

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