SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 98

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

13.4
After reset, the code in internal ROM is mapped at both addresses 0x0000_0000 and 0x0010_0000:
13.4.1
6249I–ATARM–3-Oct-11
400000
400004
400008
40000c
400010
400014
400018
40001c
DataFlash Boot
Valid Image Detection
ea000006
eafffffe
ea00002f
eafffffe
eafffffe
eafffffe
eafffffe
eafffffe
B
B
B
B
B
B
B
B
Figure 13-2. Remap Action after Download Completion
The DataFlash Boot program searches for a valid application in the SPI DataFlash memory. If a
valid application is found, this application is loaded into internal SRAM and executed by branch-
ing at address 0x0000_0000 after remap. This application may be the application code or a
second-level bootloader.
All the calls to functions are PC relative and do not use absolute addresses.
The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corre-
sponding to the ARM exception vectors. These bytes must implement ARM instructions for
either branch or load PC with PC relative addressing.
The sixth vector, at offset 0x14, contains the size of the image to download. The user must
replace this vector with his own vector (see
Figure 13-3. LDR Opcode
Figure 13-4. B Opcode
Unconditional instruction: 0xE for bits 31 to 28.
31
31
1
1
1
1
0x20
0x04
_main
0x0c
0x10
0x14
0x18
0x1c
1
1
28 27
28 27
0
0
0x0000_0000
0x0030_0000
0
1
1
0
1
I
24 23
24 23
P
0
U
Internal
Internal
SRAM
ROM
0
00ea000006B0x20
04eafffffeB0x04
08ea00002fB_main
0ceafffffeB0x0c
10eafffffeB0x10
14eafffffeB0x14
18eafffffeB0x18
1ceafffffeB0x1c
W 1
20 19
“Structure of ARM Vector 6” on page
Rn
REMAP
16 15
Offset (24 bits)
Rd
Internal
Internal
SRAM
ROM
12 11
Addressing Mode
AT91SAM9263
0x0000_0000
0x0040_0000
99).
0
0
98