SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 286

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

286
AT91SAM9263
Figure 25-9. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
a. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete inter-
b. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt
rupt is un-masked (DMAC_MaskBlock[x] = 1’b1, where x is the channel number)
hardware sets the block complete interrupt when the block transfer has completed.
It then stalls until the block complete interrupt is cleared by software. If the next
block is to be the last block in the DMA transfer, then the block complete ISR (inter-
rupt service routine) should clear the reload bits in the DMAC_CFGx.RELOAD_SR
and DMAC_CFGx.RELOAD_DS registers. This put the DMAC into Row 1 as
shown in
transfer, then the reload bits should remain enabled to keep the DMAC in Row 4.
is masked (DMAC_MaskBlock[x] = 1’b0, where x is the channel number), then
hardware does not stall until it detects a write to the block complete interrupt clear
register but starts the next block transfer immediately. In this case software must
clear the reload bits in the DMAC_CFGx.RELOAD_SR and
DMAC_CFGx.RELOAD_DS registers to put the DMAC into ROW 1 of
on page 277
is similar to that shown in
in
Figure 25-10 on page
Source Layer
Address of
Table 25-2 on page
SAR
before the last block of the DMA transfer has completed. The transfer
Source Blocks
287.
Figure 25-9 on page
277. If the next block is not the last block in the DMA
Block2
Block1
Block0
BlockN
Destination Blocks
286. The DMA transfer flow is shown
Destination Layer
DAR
Address of
6249I–ATARM–3-Oct-11
Table 25-2