SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1079

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.3.12
50.3.12.1
50.3.13
50.3.13.1
6249I–ATARM–3-Oct-11
SDRAM Controller
Static Memory Controller (SMC)
Mobile SDRAM Device Initialization Constraint
SMC Chip Select Parameters Modification
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters while fetching the code
from a memory on CS0, may lead to unpredictable behavior.
soft_user_reset
;disable IRQs
;change refresh rate to block all data accesses
;prepare power down command
;prepare proc_reset and periph_reset
;perform power down command
;perform proc_reset and periph_reset (in the ARM pipeline)
Problem Fix/Workaround
INCLUDEAT91SAM9xxx.inc
EXPORTsoft_user_reset
MRS r0, CPSR
ORR r0, r0, #0x80
MSR CPSR_c, r0
LDR r0, =AT91C_SDRAMC_TR
LDR r1, =1
STR r1, [r0]
LDR r0, =AT91C_SDRAMC_LPR
LDR r1, =2
LDR r2, =AT91C_RSTC_RCR
LDR r3, =0xA5000005
STR r1, [r0]
STR r3, [r2]
END
AT91SAM9263
1079