SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 22

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1
8.1.1
8.1.1.1
22
Embedded Memories
AT91SAM9263
Internal Memory Mapping
Internal 80 Kbyte Fast SRAM
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High Performance Bus (AHB) for its master and slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to
9 are directed to the EBI0 that associates these banks to the external chip selects EBI0_NCS0
to EBI0_NCS5 and EBI1_NCS0 to EBI1_NCS2. The bank 0 is reserved for the addressing of the
internal memories, and a second level of decoding provides 1M bytes of internal memory area.
Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus
(APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each master has its own bus and its own decoder, thus allowing a different memory mapping for
each master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot and one after remap. Refer to
details.
A complete memory map is presented in
Table 8-1
BMS state at reset.
Table 8-1.
The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split
into three areas. Its memory mapping is presented in
0x0000 0000
• 128 Kbyte ROM
• One 80 Kbyte Fast SRAM
• 16 Kbyte Fast SRAM
• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block
anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
– Single Cycle Access at full matrix speed
– Single Cycle Access at full matrix speed
– Supports ARM926EJ-S TCM interface at full processor speed
– Allows internal Frame Buffer for up to 1/4 VGA 8 bpp screen
– Single Cycle Access at full matrix speed
summarizes the Internal Memory Mapping, depending on the Remap status and the
Internal Memory Mapping
Address
Table 8-1, “Internal Memory Mapping,” on page 22
REMAP = 0
BMS = 1
ROM
Figure 8-1 on page
Figure 8-1 on page
BMS = 0
EBI0_NCS0
21.
21.
REMAP = 1
SRAM C
6249I–ATARM–3-Oct-11
for