SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1083

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.3.19
50.3.19.1
50.3.20
50.3.20.1
50.3.20.2
6249I–ATARM–3-Oct-11
UDP
UHP
Bad Data in the First IN Data Stage
Non-ISO IN Transfers
ISO OUT Transfers
The STOP is not generated.
The line shows: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
Insert a delay of one TWI clock period before step 4.
All or part of the data of the first IN data Stage are not transmitted. It may then be a Zero Length
Packet. The CRC is correct. Thus the HOST may only see that the size of the received data
does not match the requested length. But even if performed again, the control transfer probably
fails.
Control transfers are mainly used at device configuration. After clearing RXSETUP, the software
needs to compute the setup transaction request before writing data into the FIFO if needed. This
time is generally greater than the minimum safe delay required above. If not, a software wait
loop after RXSETUP clear may be added at minimum cost.
Conditions:
Consider the following scenario:
Consequence: When this error occurs, the Host controller tries the same IN token again.
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following scenario:
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to do two Write transactions (TD status write and
5. Host controller raises the request for the first write transaction. By the time the transac-
6. After completing the first write transaction, the Host controller skips the second write
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
TD retirement write) to the system memory in order to complete the status update.
tion is completed, a frame boundary is crossed.
transaction.
AT91SAM9263
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