SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1081
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 1081 of 1109
- Download datasheet (17Mb)
50.3.14.6
50.3.14.7
50.3.14.8
50.3.15
50.3.15.1
50.3.15.2
50.3.15.3
6249I–ATARM–3-Oct-11
Serial Synchronous Controller (SSC)
SPI: SPI Software Reset Must Be Written Twice
SPI: Chip Select and Fixed Mode
SPI: Software Reset Must be Written Twice
Transmitter Limitations in Slave Mode
Periodic Transmission Limitations in Master Mode
Unexpected Delay on TD output
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly
set.
None.
In fixed Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip
Select 0, the output spi_size sampled by the PDC depends on the field BITS of SPI_CSR0 reg-
ister, whatever the selected Chip select may be. For example, if CSR0 is configured for a 10-bit
transfer, whereas the CSR1 is configured for an 8-bit transfer, when a transfer is performed in
Fixed mode through the PDC on Chip Select 1, the transfer is considered to be a half-word
transfer.
If a PDC transfer has to be performed in 8 bits on a Chip select y (y different from 0), the field
BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy
Register.
If a software reset (SWRST in the control register) is performed, the SPI may not work properly
(the clock is enabled before the chip select).
The SPI Control Register field, SWRST (Software Reset) needs to be written twice to be cor-
rectly set.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
If Last Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
None.
When SSC is configured with the following conditions:
An unexpected delay of 2 or 3 system clock cycles is added to TD output.
• TCMR.STTDLY more than 0
• RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge
• RFMR.FSOS = None (input)
• TCMR.START = Receive Start
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9263
1081
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