SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1080

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.3.14
50.3.14.1
50.3.14.2
50.3.14.3
50.3.14.4
50.3.14.5
1080
AT91SAM9263
Serial Peripheral Interface (SPI)
SPI: Pulse Generation on SPCK
SPI: Bad PDC Behavior when CSAAT=1 and SCBR = 1
SPI: LASTXFER (Last Transfer) Behavior
SPI: Baudrate Set to 1
SPI: Software Reset
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
None.
If the SPI2 is programmed with CSAAT = 1, SCBR (baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
None. Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode with CSAAT bit set and in PDC Mode, the Chip Select can rise depending on the
data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a
"1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY
flag is set.
Use the CS in PIO mode when PDC Mode is required and CS has to be maintained between
transfers.
When Baudrate is set to 1 (i.e. when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No such pulse occurs if BITS
field equals 8,10,12,14 or 16 and Baudrate = 1.
None.
If the Software reset command is performed during the same clock cycle as an event for
TXRDY, there is no reset.
Perform another a software reset.
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0.
6249I–ATARM–3-Oct-11