SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 313

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.4.9
Name: DMAC_DSRx
Addresses:0x00800050 [0], 0x008000A8 [1]
Access: Read-write
Reset: 0x0
The address offset for each channel is: 0x50+[x * 0x58]
For example, DSR0: 0x050, DSR1: 0x0a8, etc.
The DMAC_CTLx.DINC field controls whether the address increments or decrements. When the DMAC_CTLx.DINC field
indicates a fixed address control then the address remains constant throughout the transfer and the DMAC_DSRx register
is ignored.
• DSI: Destination Scatter Interval
Destination scatter interval field (DMAC_DSRx.DSI) – specifies the destination address increment/decrement in multiples
of DMAC_CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer.
• DSC: Destination Scatter Count
Destination scatter count field (DMAC_DSRx.DSC) – specifies the number of contiguous destination transfers of
DMAC_CTLx.DST_TR_WIDTH between successive scatter boundaries.
6249I–ATARM–3-Oct-11
31
23
15
–
7
Destination Scatter Register for Channel x
30
22
14
–
6
DSC
29
21
13
–
5
28
20
12
–
4
DSI
DSI
27
19
11
–
3
26
18
10
–
2
DSI
AT91SAM9263
25
17
–
9
1
24
16
–
8
0
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