SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1068

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.2.15.9
50.2.16
50.2.16.1
50.2.16.2
50.2.16.3
50.2.16.4
50.2.17
50.2.17.1
1068
AT91SAM9263
Serial Synchronous Controller (SSC)
System Controller
SPI: Software Reset Must be Written Twice
Transmitter Limitations in Slave Mode
Periodic Transmission Limitations in Master Mode
SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer
Possible Event Loss when Reading RTT_SR
If a software reset (SWRST in the control register) is performed, the SPI may not work properly
(the clock is enabled before the chip select).
The SPI Control Register field, SWRST (Software Reset) needs to be written twice to be cor-
rectly set.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
If Last Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
None.
When the SSC receiver is used with the following conditions:
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
None.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when RTT_SR is
read, the corresponding bit may be cleared. This may lead to the loss of this event.
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6249I–ATARM–3-Oct-11