SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 626
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 626 of 1109
- Download datasheet (17Mb)
36.6.4.5
36.6.4.6
36.6.4.7
626
AT91SAM9263
AC97 Codec Reset
Cold AC97 Reset
Warm AC97 Reset
The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the
controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously
(regarding AC97FS) detected by the AC97 Controller. If WKUP bit is enabled in AC97C_IMR
register, an interrupt is triggered that wakes up the AC97 Controller which should then immedi-
ately issue a cold or a warm reset.
If the processor needs to be awakened by an external event, the AC97RX signal must be exter-
nally connected to the WAKEUP entry of the system controller.
Figure 36-7. AC97 Power-Down/Up Sequence
There are three ways to reset an AC97 Codec.
A cold reset is generated by asserting the RESET signal low for the minimum specified time
(depending on the AC97 Codec) and then by de-asserting RESET high. AC97CK and AC97FS
is reactivated and all AC97 Codec registers are set to their default power-on values. Transfers
on AC-link can resume.
The RESET signal will be controlled via a PIO line. This is how an application should perform a
cold reset:
AC97CK, the clock provided by AC97 Codec, is detected by the controller.
A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is sig-
naled by driving AC97FX signal high for a minimum of 1us in the absence of AC97CK. In the
absence of AC97CK, AC97FX is treated as an asynchronous (regarding AC97FX) input used to
signal a warm reset to AC97 Codec.
This is the right way to perform a warm reset:
• Clear and set ENA flag in the AC97C_MR register to reset the AC97 Controller
• Clear PIO line output controlling the AC97 RESET signal
• Wait for the minimum specified time
• Set PIO line output controlling the AC97 RESET signal
• Set WRST in the AC97C_MR register.
• Wait for at least 1us
• Clear WRST in the AC97C_MR register.
AC97CK
AC97RX
AC97FS
AC97TX
TAG
TAG
Power Down Frame
Write to
Write to
0x26
0x26
Data
Data
PR4
PR4
Sleep State
Wake Event
Warm Reset
TAG
TAG
New Audio Frame
6249I–ATARM–3-Oct-11
Slot1
Slot1
Slot2
Slot2
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