SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 279

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.3.4.6
25.3.5
25.3.5.1
25.3.5.2
6249I–ATARM–3-Oct-11
Programming a Channel
Ending Multi-block Transfers
Programming Examples
Single-block Transfer (Row 1)
All multi-block transfers must end as shown in Row 1 of
every block transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous block transferred was the last block and the DMA transfer is terminated.
F o r r o w s 2 , 3 a n d 4 o f
DMAC_CFGx.RELOAD_SR and/or DMAC_CFGx.RELOAD_DS is set), multi-block DMA trans-
fers continue until both the DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS
registers are cleared by software. They should be programmed to zero in the end of block inter-
rupt service routine that services the next-to-last block transfer. This puts the DMAC into Row 1
state.
Note:
Three registers, the DMAC_LLPx, the DMAC_CTLx and DMAC_CFGx, need to be programmed
to set up whether single or multi-block transfers take place, and which type of multi-block trans-
fer is used. The different transfer types are shown in
The “Update Method” column indicates where the values of DMAC_SARx, DMAC_DARx,
DMAC_CTLx, and DMAC_LLPx are obtained for the next block transfer when multi-block DMAC
transfers are enabled.
Note:
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing
3. Program the following channel registers:
to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock,
DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt
Raw Status and Interrupt Status registers confirms that all interrupts have been
cleared.
a. Write the starting source address in the DMAC_SARx register for channel x.
b. Write the starting destination address in the DMAC_DARx register for channel x.
c. Program DMAC_CTLx and DMAC_CFGx according to Row 1 as shown in
d. Write the control information for the DMA transfer in the DMAC_CTLx register for
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the TT_FC of the DMAC_CTLx
register.
For rows 6, 8, and 10 (both DMAC_CFGx.RELOAD_SR and
DMAC_CFGx.RELOAD_DS cleared) the user must setup the last block descriptor in
memory such that both LLI.DMAC_CTLx.LLP_S_EN and LLI.DMAC_CTLx.LLP_D_EN
are zero.For rows 7 and 9, the end-of-block interrupt service routine that services the
next-to-last block transfer should clear the DMAC_CFGx.RELOAD_SR and
DMAC_CFGx.RELOAD_DS reload bits. The last block descriptor in memory should be
set up so that both the LLI.DMAC_CTLx.LLP_S_EN and LLI.DMAC_CTLx.LLP_D_EN
are zero.
In
DMAC_CTLx.LLP_S_EN, DMAC_CFGx.RELOAD_SR, DMAC_CTLx.LLP_D_EN, and
DMAC_CFGx.RELOAD_DS are illegal, and causes indeterminate or erroneous behavior.
25-2 on page
channel x. For example, in the register, you can program the following:
Table 25-2 on page
277. Program the DMAC_LLPx register with ‘0’.
277, all other combinations of DMAC_LLPx.LOC = 0,
T a b l e 2 5 - 2 o n p a g e 2 7 7
Table 25-2 on page
Table 25-2 on page
, ( D M A C _ L L P x = 0 a n d
AT91SAM9263
277.
277. At the end of
Table
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