SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 276

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.3.4.1
25.3.4.2
Figure 25-5. Multi-block Transfer Using Linked Lists
276
AT91SAM9263
LLPx(0)
Multi-block Transfers
Block Chaining Using Linked Lists
CTLx[63..32]
CTLx[31..0]
LLPx(1)
DARx
SARx
In this case, the DMAC re-programs the channel registers prior to the start of each block by
fetching the block descriptor for that block from system memory. This is known as an LLI update.
DMAC block chaining is supported by using a Linked List Pointer register (DMAC_LLPx) that
stores the address in memory of the next linked list item. Each LLI (block descriptor) contains
the corresponding block descriptor (DMAC_SARx, DMAC_DARx, DMAC_LLPx, DMAC_CTLx).
To set up block chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx registers are fetched from
system memory on an LLI update.
to define multi-block transfers using block chaining.
The Linked List multi-block transfers is initiated by programming DMAC_LLPx with LLPx(0)
( L L I ( 0 ) b a s e a d d r e s s ) a n d D M AC _ C T L x w i t h D M A C _ C T L x . L L P _ S _ E N a n d
DMAC_CTLx.LLP_D_EN.
LLI(0)
System Memory
LLPx(1)
Figure 25-5
CTLx[63..32]
CTLx[31..0]
LLPx(2)
DARx
SARx
shows how to use chained linked lists in memory
LLI(1)
LLPx(2)
6249I–ATARM–3-Oct-11