SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1082

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.3.16
50.3.16.1
50.3.17
50.3.17.1
50.3.18
50.3.18.1
50.3.18.2
50.3.18.3
50.3.18.4
1082
AT91SAM9263
Pulse Width Modulation (PWM)
System Controller
Two-wire Interface (TWI)
Zero Period
Possible Event Loss when Reading RTT_SR
Clock Divider
Disabling Does Not Operate Correctly
Software Reset
STOP not Generated
None.
It is impossible to update a period equal to 0 by using the PWM_CUPD register.
None.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when RTT_SR is
read, the corresponding bit may be cleared. This may lead to the loss of this event.
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
The value of CLDIV x 2
must be less than or equal to 8191·
None.
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with
the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register
(TWI_SR) are not reset.
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts
must be disabled before disabling the TWI.
When a software reset is performed during a frame and when TWCK is low, it is impossible to
initiate a new transfer in READ or WRITE mode.
None.
If the sequence described as follows occurs:
1. WRITE 1 or more bytes at a given address.
2. Send a STOP.
3. Wait for TXCOMP flag.
4. READ (or WRITE) 1 or more bytes at the same address.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
6249I–ATARM–3-Oct-11
CKDIV