SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 902

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

44.5.2.3
902
AT91SAM9263
FIFO
The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The
parameter initial_latency is defined as the number of LCDC Core Clock cycles until the first data
is available at the output of the datapath. The parameter cycles_per_data is the minimum num-
ber of LCDC Core clock cycles between two consecutive data at the output interface.
These parameters are different for the different configurations of the LCD Controller and are
shown in
Table 44-2.
The FIFO block buffers the input data read by the DMA module. It contains two input FIFOs to
be used in Dual Scan configuration that are configured as a single FIFO when used in single
scan configuration.
The size of the FIFOs allows a wide range of architectures to be supported.
The upper threshold of the FIFOs can be configured in the FIFOTH field of the LCDFIFO regis-
ter. The LCDC core will request a DMA transfer when the number of words in each FIFO is less
than FIFOTH words. To avoid overwriting in the FIFO and to maximize the FIFO utilization, the
FIFOTH should be programmed with:
where:
TFT
STN Mono
STN Mono
STN Mono
STN Mono
STN Color
STN Color
STN Color
STN Color
• The output interface is a 24-bit data bus. The configuration of this interface depends on the
• The configuration interface connects the datapath with the configuration block. It is used to
• The control interface connects the datapath with the timing generation block. The main
• 2048 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode
• DMA_burst_length is the burst length of the transfers made by the DMA
type of LCD used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface).
select between the different datapath configurations.
control signal is the data-request signal, used by the timing generation module to request
new data from the datapath.
and half that size in dual scan mode.
DISTYPE
FIFOTH = 2048 - (2 x DMA_BURST_LENGTH + 3)
Table
Datapath Parameters
44-2.
SCAN
Single
Single
Dual
Dual
Single
Single
Dual
Dual
Configuration
IFWIDTH
4
8
8
16
4
8
8
16
initial_latency
9
13
17
17
25
11
12
14
15
1
4
8
8
16
2
3
4
6
cycles_per_data
6249I–ATARM–3-Oct-11