SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 23

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 8-2.
Table 8-3.
6249I–ATARM–3-Oct-11
Decoded
Area
SRAM A
SRAM B
(DTCM)
Internal
Internal
(ITCM)
Internal SRAM B
(DTCM) size
Address
0x0010 0000
0x0010 4000
0x0020 0000
0x0020 4000
Internal SRAM Block Size
16 Kbyte Block Allocation
Internal SRAM C
0
16 Kbytes
32 Kbytes
Within the 80 Kbytes of SRAM available, the amount of memory assigned to each block is soft-
ware programmable as a multiple of 16 Kbytes as shown in
size of the Internal SRAM C according to the size of the internal SRAM A and the internal SRAM
B.
Note that among the five 16 Kbyte blocks making up the Internal SRAM, one is permanently
assigned to Internal SRAM C.
At reset, the whole memory (80 Kbytes) is assigned to Internal SRAM C.
The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and
when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block
organization may affect the previous configuration from a software point of view.
Table 8-3
to RB4).
• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block
• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap
configuration register located in the Chip Configuration User Interface. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0010 0000.
anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0020 0000.
Command is performed, this SRAM block is accessible through the AHB bus at address
0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes
accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926
Data Masters.
Configuration examples and related 16 Kbyte block assignments
ITCM = 0 Kbyte
DTCM = 0 Kbyte
AHB = 80 Kbytes
illustrates different configurations and the related 16 Kbyte blocks assignments (RB0
(1)
ITCM = 32 Kbytes
DTCM = 32 Kbytes
AHB = 16 Kbytes
0
80 Kbytes
64 Kbytes
48 Kbytes
RB1
RB0
RB3
RB2
ITCM = 16 Kbytes
DTCM = 32 Kbytes
AHB = 32 Kbytes
Internal SRAM A (ITCM) Size
RB1
RB3
RB2
16 Kbytes
64 Kbytes
48 Kbytes
32 Kbytes
ITCM = 32 Kbytes
DTCM = 16 Kbytes
AHB = 32 Kbytes
Table
RB1
RB0
RB3
8-2. This table provides the
AT91SAM9263
32 Kbytes
48 Kbytes
32 Kbytes
16 Kbytes
ITCM = 16 Kbytes
DTCM = 16 Kbytes
AHB = 48 Kbytes
RB1
RB3
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