SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1084

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

50.3.20.3
50.3.21
50.3.21.1
50.3.21.2
1084
AT91SAM9263
USART
Remote Wakeup Event
RXBRK Flag Error in Asynchronous Mode
RTS not Expected Behavior
Consequence: After the failure condition, the Host controller stops sending the SOF. This
causes the connected device to go into suspend state.
This problem can be avoided if the system can guarantee that no buffer underrun occurs during
the transfer.
Conditions:
When a Remote Wakeup event occurs on a downstream port, the OHCI Host controller begins
to send resume signaling to the device. The Host controller should send this resume signaling
for 20 ms. However, if the driver sets the HcControl.HCFS into USBOPERATIONAL state during
the resume event, then the Host controller terminates sending the resume signal with an EOP to
the device.
Consequence: If the Device does not recognize the resume (<20 ms) event then the Device, it
will remain in the suspend state.
Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL.
When timeguard is 0, RXBRK is not set when the break character is located just after the Stop
Bit. FRAME (Frame Error) is set instead.
Timeguard should be > 0.
None.
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the
2. When the Host controller is sending the ISO OUT data, because of system latencies,
3. While there is an underrun condition, if the Host controller is in the process of bit-stuff-
1. Setting the receiver to hardware handshaking mode drops RTS line to low level even if
2. Disabling the receiver during a PDC transfer while RXBUFF flag is '0' has no effect on
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
system memory.
remaining bytes of the packet are not available. This results in a buffer underrun
condition.
ing, it causes the Host controller to hang.
the receiver is still turned off. USART needs to be completely configured and started
before setting the receiver to hardware handshaking mode.
RTS. The only way to get the RTS line to rise to high level is to reset both PDMA buffers
by writing the value '0' in both counter registers.
6249I–ATARM–3-Oct-11