SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1066
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 1066 of 1109
- Download datasheet (17Mb)
50.2.14
50.2.14.1
50.2.15
50.2.15.1
50.2.15.2
50.2.15.3
50.2.15.4
1066
AT91SAM9263
Static Memory Controller (SMC)
Serial Peripheral Interface (SPI)
SMC Chip Select Parameters Modification
SPI: PDC Data Loss
SPI: Pulse Generation on SPCK
SPI: Bad PDC Behavior when CSAAT=1 and SCBR = 1
SPI: LASTXFER (Last Transfer) Behavior
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters while fetching the code
from a memory on CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select.
One byte data can be lost when PDC transmits. This occurs when write accesses are performed
on the base address of any peripheral, during the PDC transfer.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
None.
If the SPI2 is programmed with CSAAT = 1, SCBR (baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
None. Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode with CSAAT bit set and in PDC Mode, the Chip Select can rise depending on the
data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a
"1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY
flag is set.
Problem Fix/Workaround:
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
– Add a timeout for the PDC transfer and check the value of the PDC transmit counter
– Check the data integrity by a checksum.
– Avoid write access on the base address of peripherals during a PDC transfer.
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0.
when the timeout elapsed.
6249I–ATARM–3-Oct-11
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