SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 914

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

914
AT91SAM9263
An 8-bit single scan STN display uses 8 parallel data lines to shift data to successive single hor-
izontal lines one at a time until the entire frame has been shifted and transferred. The 8 LSB pins
of LCD Data Bus (LCDD [7:0]) can be directly connected to the LCD driver; the 16 MSB pins
(LCDD [23:8]) are not used.
An 8-bit Dual Scan STN display uses two sets of 4 parallel data lines to shift data to successive
upper and lower panel horizontal lines one at a time until the entire frame has been shifted and
transferred. The bus LCDD[3:0] is connected to the upper panel data lines and the bus
LCDD[7:4] is connected to the lower panel data lines. The rest of the LCD Data Bus lines
(LCDD[23:8]) are not used.
A 16-bit Dual Scan STN display uses two sets of 8 parallel data lines to shift data to successive
upper and lower panel horizontal lines one at a time until the entire frame has been shifted and
transferred. The bus LCDD[7:0] is connected to the upper panel data lines and the bus
LCDD[15:8] is connected to the lower panel data lines. The rest of the LCD Data Bus lines
(LCDD[23:16]) are not used.
STN Mono displays require one bit of image data per pixel. STN Color displays require three bits
(Red, Green and Blue) of image data per pixel, resulting in a horizontal shift register of length
three times the number of pixels per horizontal line. This RGB or Monochrome data is shifted to
the LCD driver as consecutive bits via the parallel data lines.
A TFT single scan display uses up to 24 parallel data lines to shift data to successive horizontal
lines one at a time until the entire frame has been shifted and transferred. The 24 data lines are
divided in three bytes that define the color shade of each color component of each pixel. The
LCDD bus is split as LCDD[23:16] for the blue component, LCDD[15:8] for the green component
and LCDD[7:0] for the red component. If the LCD Module has lower color resolution (fewer bits
per color component), only the most significant bits of each component are used.
All these interfaces are shown in
the 24-bit single scan TFT display timing;
STN display timing for monochrome and color modes;
single scan STN display timing for monochrome and color modes;
shows the 8-bit Dual Scan STN display timing for monochrome and color modes;
on page 918
Figure 44-6. TFT Timing (First Line Expanded View)
shows the 16-bit Dual Scan STN display timing for monochrome and color modes.
LCDVSYNC
LCDDEN
LCDHSYNC
LCDDOTCK
LCDD [24:16]
LCDD [15:8]
LCDD [7:0]
Figure 44-6
Figure 44-7 on page 915
B0
G0
R0
to
B1
G1
R1
Figure
Figure 44-8 on page 916
44-10.
Figure 44-6 on page 914
shows the 4-bit single scan
Figure 44-9 on page 917
6249I–ATARM–3-Oct-11
shows the 8-bit
Figure 44-10
shows