SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1091

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6249I–ATARM–3-Oct-11
Revision
6249E
Comments (Continued)
SDRAMC:
Section 23.6.1 ”SDRAMC Mode
SDRAMC Configuration Register
SHDWC:
Table 18-1, ”Shutdown Controller Block
SMC:
Section 22.14 ”Programmable IO
Section 22.8.5 ”Coding Timing
Table 22-4 on page
Section 22.9.3.1 ”User
added.
SPI:
Section 32.7.9 ”SPI Chip Select
BITS bitfield description and
SSC:
Section 35.8.3 ”SSC Receive Clock Mode
TC:
Section 39.6 ”Timer Counter (TC) User
channel registers indexed and referenced in the register tables that follow. Functional value of WAVE is given.
Section 39.6.2 ”TC Block Mode
Section 39.6.4 ”TC Channel Mode Register: Capture
TDGC:
All mention of Polygon Fill feature removed. Fill Control Register, Vertex X, Vertex Y registers removed from
User Interface, addresses reassigned as “Reserved” in,
User Interface: 2D Graphics Controller (2DGC) replaced by Two D Graphics Controller (TDGC).
Section 45.5.23 ”VRAM Size
Section 45.5.4 ”Source/Begin Y
Section 45.5.15 ”Extended End Y
Table title number removed from tables in bitfield descriptions.
TWI:
Section 33. ”Two-wire Interface
205.
Procedure”, Instructions regarding configuration parameters of SMC Chip Select
Section 32.6.4 ”SPI Slave Mode”
Register”, VSIZE field (updated with explicit hex radix).
Parameters”, “Effective Value” column under “Permitted Range” updated in
Register”, typo fixed in bit fields 2 and 3.
(TWI)”, the implementation of the TWI has been updated in this product.
Register”, note pertaining to BITS field added. This note is referenced in the
Register”, typo “YCOR” fixed, = “YSRC”.
Register”; changed MODE bit description.
“CAS: CAS Latency” on page
Delays”, added to datasheet
Register”, typo EXT_BY fixed, = “EXT_EY”.
Interface”, Register mapping consolidated into one table, offsets of
Diagram”; corrected register names in the block diagram.
Register”, corrected bit name to STTDLY.
Mode”, bit field 15 updated.
Table 45-2, “TDGC Register Mapping,” on page
250, changed CAS bit description
AT91SAM9263
971.
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