SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1010

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.4.3
Name:
Address:
Access:
Reset:
• SOF: Start of frame
0: No start of frame has been detected.
1: A start of frame has been detected.
• DIS: Image Sensor Interface disable
0: The image sensor interface is enabled.
1: The image sensor interface is disabled and stops capturing data. The DMA controller and the core can still read the
FIFOs.
• SOFTRST: Software reset
0: Software reset not asserted or not completed.
1: Software reset has completed successfully.
• CDC_PND: Codec request pending
0: No request asserted.
1: A codec request is pending. If a codec request is asserted during a frame, the CDC_PND bit rises until the start of a new
frame. The capture is completed when the flag FO_C_EMP = 1.
• CRC_ERR: CRC synchronization error
0: No crc error in the embedded synchronization frame (SAV/EAV)
1: The CRC_SYNC is enabled in the control register and an error has been detected and not corrected. The frame is dis-
carded and the ISI waits for a new one.
• FO_C_OVF: FIFO codec overflow
0: No overflow
1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an
attempt is made to write a new sample to the FIFO.
1010
FO_P_EMP
31
23
15
–
–
–
7
AT91SAM9263
ISI Status Register
0xFFFC4008
ISI_SR
Read
0x0
FO_P_OVF
30
22
14
–
–
–
6
FO_C_OVF
29
21
13
–
–
–
5
CRC_ERR
28
20
12
–
–
–
4
CDC_PND
27
19
11
–
–
–
3
SOFTRST
26
18
10
–
–
–
2
FR_OVR
DIS
25
17
–
–
9
1
6249I–ATARM–3-Oct-11
FO_C_EMP
SOF
24
16
–
–
8
0