SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 288

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

288
AT91SAM9263
Note:
Note:
3. Write the starting source address in the DMAC_SARx register for channel x.
4. Write the channel configuration information into the DMAC_CFGx register for channel
5. Make sure that the LLI.DMAC_CTLx register locations of all LLIs in memory (except the
6. Make sure that the LLI.DMAC_LLPx register locations of all LLIs in memory (except the
7. Make sure that the LLI.DMAC_DARx register location of all LLIs in memory point to the
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register loca-
9. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx
10. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx
11. Clear any pending interrupts on the channel from the previous DMA transfer by writing
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 7 as shown in
13. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked
14. Finally, enable the channel by writing a ‘1’ to the DMAC_ChEnReg.CH_EN bit. The
15. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
16. Source and destination request single and burst DMAC transactions to transfer the
– vi. Incrementing/decrementing or fixed address for destination DINC field.
x.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
last) are set as shown in Row 7 of
register of the last Linked List item must be set as described in Row 1 of
Figure 25-8 on page 284
last) are non-zero and point to the next Linked List Item.
start destination block address proceeding that LLI fetch.
tions of all LLIs in memory is cleared.
register for channel x.
register for channel x.
to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock,
DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt
Raw Status and Interrupt Status registers confirms that all interrupts have been
cleared.
Table 25-2 on page
List item.
transfer is performed. Make sure that bit 0 of the DMAC_DmaCfgReg register is
enabled.
block of data (assuming non-memory peripherals). DMAC acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block
transfer.
The values in the LLI.DMAC_SARx register locations of each of the Linked List Items (LLIs) setup
up in memory, although fetched during a LLI fetch, are not used.
The LLI.DMAC_SARx, LLI.DMAC_DARx, LLI. DMAC_LLPx and LLI.DMAC_CTLx registers are
fetched. The LLI.DMAC_SARx register although fetched is not used.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
277.
shows a Linked List example with two list items.
Table 25-2 on page 277
while the LLI.DMAC_CTLx
6249I–ATARM–3-Oct-11
Table
25-2.