SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 483

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 33-9. Master Read with One Data Byte
Figure 33-10. Master Read with Multiple Data Bytes
33.8.6
33.8.6.1
483
TXCOMP
RXRDY
TWD
AT91SAM9263
Internal Address
S
7-bit Slave Addressing
Write START Bit
DADR
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 33-11
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
TXCOMP
RXRDY
R
TWD
A
and
S
DATA n
Write START &
Figure 33-13
STOP Bit
DADR
Figure
Read RHR
A
DATA n
33-10. For Internal Address usage see
for Master Write operation with internal address.
DATA (n+1)
R
A
A
DATA (n+1)
Read RHR
DATA
DATA (n+m)-1
Figure
Read RHR
N
33-9. When a multiple data byte read is
DATA (n+m)-1
P
A
Read RHR
after next-to-last data read
DATA (n+m)
Write STOP Bit
Section
Figure
33.8.6.
6249I–ATARM–3-Oct-11
N
33-12. See
DATA (n+m)
Read RHR
P