SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 20

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.8
20
Debug and Test Features
AT91SAM9263
• Transfer Initiation
• Interrupt
• ARM926 Real-time In-circuit Emulator
• Debug Unit
• Embedded Trace Macrocell: ETM9
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
– Suspend DMA operation
– Programmable DMA lock transfer support.
– Supports four external DMA Requests
– Support for software handshaking interface. Memory mapped registers can be used
– Programmable interrupt generation on DMA transfer completion, Block transfer
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
– Medium+ Level Implementation
– Half-rate Clock Mode
– Four Pairs of Address Comparators
– Two Data Comparators
– Eight Memory Map Decoder Inputs
– Two 16-bit Counters
– One 3-stage Sequencer
– One 45-byte FIFO
to control the flow of a DMA transfer in place of a hardware handshaking interface
completion, Single/Multiple transaction completion or Error condition
™
6249I–ATARM–3-Oct-11