SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 275

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 25-4. External DMA Request Timing
25.3.4
6249I–ATARM–3-Oct-11
nDMAREQx
dma_ack
dma_req
DMAC Transfer Types
Hclk
Each DMAREQx assertion leads to a transfer. Its size (given by CTLxL.SRC_MSIZE and
CTLxL.DEST_MSIZE) is decremented from CTLxH.BLOCK_TS.
The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted
again before a new transaction starts. The DMA ends the current transfer.
For a source FIFO, an active edge is triggered on nDMAREQx when the source FIFO exceeds a
watermark level. For a destination FIFO, an active edge is triggered on nDMAREQx when the
destination FIFO drops below the watermark level.
The source transaction length, CTLxL.SRC_MSIZE, and destination transaction length,
CTLxL.DEST_MSIZE, must be set according to watermark levels on the source/destination
peripherals.
A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multi-
block transfer, the DMAC_SARx/DMAC_DARx register in the DMAC is reprogrammed using
either of the following methods:
On successive blocks of a multi-block transfer, the DMAC_CTLx register in the DMAC is re-pro-
grammed using either of the following methods:
When block chaining, using linked lists is the multi-block method of choice, and on successive
blocks, the DMAC_LLPx register in the DMAC is re-programmed using the following method:
A block descriptor (LLI) consists of following registers, DMAC_SARx, DMAC_DARx,
DMAC_LLPx, DMAC_CTLx. These registers, along with the DMAC_CFGx register, are used by
the DMAC to set up and describe the block transfer.
• Block chaining using linked lists
• Auto-reloading
• Contiguous address between blocks
• Block chaining using linked lists
• Auto-reloading
• Block chaining using linked lists
DMA Transfers
DMA Transaction
DMA Transfers
DMA Transfers
AT91SAM9263
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