SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 327

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.4.23
Name: DMAC_ChEnReg
Address:0x008003A0
Access: Read-write
Reset: 0x0
• CH_ENx:
0 = Disable the Channel
1 = Enable the Channel
Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.
The DMAC_ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer
of the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer
has completed.
• CH_EN_WEx:
The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on
the same AMBA write transfer.
For example, writing 0x101 writes a 1 into DMAC_ChEnReg[0], while DMAC_ChEnReg[7:1] remains unchanged.
6249I–ATARM–3-Oct-11
31
23
15
–
–
–
7
–
DMAC Channel Enable Register
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
CH_EN_WE1
AT91SAM9263
CH_EN1
25
17
–
–
9
1
CH_EN_WE0
CH_EN0
24
16
–
–
8
0
327